To manufacture electric circuits involves the formation of interconnection between devices. Thus, to fabricate ICs, interconnections and contacts from one another must be formed on the silicon substrate for electrical signal connection. The technology used to connect these isolated devices through specific electrical paths employs high conductivity, thin film structure. Therefore, a connection is needed between a conductor layer and the silicon substrate. A hole in an isolation layer must be provided to allow such contact to occur.
Up to now, many of contact technologies have been proposed. One of the most widely used materials for filling the hole is tungsten (W). W-plug is used primarily for connection between isolated devices in VLSI and ULSI. A conventional method to form the W-plug will be described as follows.
Turning to FIG. 1, a silicon substrate 2 is provided, then an isolation layer 4 is deposited on the substrate 2 for isolation. Next, a contact hole 6 is created in the isolation layer 4 by using patterning and etching processes. A titanium layer 8 is subsequently deposited on the isolation layer 4 and on the surface of the contact hole 6 using physical vapor deposition (PVD). The thickness of the titanium layer 8 is about 1000 angstroms. Such thickness of the titanium layer 8 is necessary due to the bad step coverage of the PVD process.
Referring to FIG. 2, the titanium layer 8 is then treated by rapid thermal annealing (RTA) in nitrogen ambient environment to form the TiN layer 10. The TiN layer 10 serves as the barrier for subsequent process. Further, a TiSi.sub.2 layer 12 will be simultaneously formed on the interface between the silicon substrate 2 and the titanium layer 8. The TiSi.sub.2 layer 12 is used to reduce the resistance of the contact.
Turning to FIG. 3, a tungsten layer 14 is formed by CVD on the TiN layer 10 and refilled into the contact hole 6. Next, a CMP is utilized to polish the tungsten layer 14 for planarization Unfortunately, the conventional process needs long polish time to remove the thick TiN layer 10 and the titanium 8. However, the long polish time for planarization may cause the erosion effect. Further, it also raises the cost of the CMP for removing the tungsten layer 14 in the conventional method. Additionally, the PVD titanium deposition process can not achieve high aspect ratio contact in half submicron devices.